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veripower
AI-assisted IC design flow skills — specification, RTL, lint/CDC, simulation, synthesis, timing analysis, and signoff
chipweaver8
3 results
AI-assisted IC design flow skills — specification, RTL, lint/CDC, simulation, synthesis, timing analysis, and signoff
Native SVW waveform rendering plugin for DeepSeek Harness
DSH 插件:高云 Gowin 1.9 FPGA 工具链全流程掌握 —— 环境探针、工程/约束读写校验、命令行编译(gw_sh)、烧录(programmer_cli)、报告解析、GAO 在线逻辑分析链路。纯 JS 零依赖。